The present invention relates to the art of a field-effect transistor such as a MOSFET, an IGBT, or the like.
One conventional MOSFET will be described below with reference to FIGS. 39 and 40 of the accompanying drawings.
As shown in FIG. 39, a conventional MOSFET 101 disclosed in literature comprises a drain layer 105 of single crystal of silicon and doped with a high concentration of an N+-type impurity, and an Nxe2x88x92-type conductive layer 106 deposited on the drain layer 105 by epitaxial growth. The conductive layer 106 includes base regions 112 formed by diffusing a P-type impurity from the surface thereof.
Each of the base legions 112 includes a ring-shaped source region 114 formed by diffusing an N-type impurity from the surface thereof. A channel region 115 lies between the outer end of the base region 112 and the outer peripheral edge of the source region 114.
The base region 112, the source region 114, and the channel region 115 make up one rectangular cell 117. The MOSFET 101 has a number of cells 117 that are arranged regularly in a grid-like pattern.
FIG. 40 shows the layout of the cells 117 of the MOSFET 101.
A gate insulating film 121 in the form of a silicon oxide film is disposed on the channel regions 115 of adjacent two of the cells 117 and the surface of the conductive layer 106 between those two cells 117. A gate electrode film 131 is disposed on the gate insulating film 121.
The base region 112 has a surface exposed inside of the ring shaped source region 114. An inter layer insulation film 122 is disposed on the gate electrode film 131.
Reference numeral 132 represents a part of the source electrode film deposited on the surface of the source region 114 and the base region 112 and a part deposited on the interlayer insulation film 122. Those two parts are connected each other.
The source electrode film also has a part deposited on the surface of gate electrode film 131 and is insulated from the part of the source electrode film deposited on the surface of the source region 114 and base region 112 and the part deposited on the interlayer insulation film 122.
The MOSFET 101 also has a protective film 135 disposed on the source electrode films 132. The protective film 135 and the interlayer insulation films 122 are patterned to expose portions of the source electrode films 132 and also portions of the thin metal film connected to the gate electrode films 131.
A drain electrode 133 is disposed on the surface of the drain layer 105 remotely from the conductive layer 106. The drain electrode 133, the exposed portions of the source electrode films 132, and the exposed portions of the thin metal film connected to the gate electrode films 131 are connected to respective external terminals which are connected to an electric circuit for operating the MOSFET 101.
To operate the MOSFET 101, the source electrode films 132 are placed on a ground potential, and a positive voltage is applied to the drain electrode 133. When a gate voltage (positive voltage) equal to or higher than a threshold voltage is then applied to the gate electrode films 131, an N-type inverted layer is formed on the surface of the P-type channel region 115 of each cell 117, and the source region 114 and the conductive layer 106 are connected to each other by the inverted layer, so that a current flows from the drain electrode 133 to the source electrode films 132.
When a voltage, e.g., a ground potential, lower than the threshold voltage is thereafter applied to the gate electrode films 131, the inverted layer is eliminated, and the base regions 112 and the conductive layer 106 are reverse-biased, so that no current flows between the drain electrode 133 and the source electrode films 132.
Therefore, the drain electrode 133 and the source electrode films 132 can be connected to each other or disconnected from each other by controlling the voltage applied to the gate electrode films 131. The MOSFET 101 is widely used as a high-speed switch in power electric circuits such as power supply circuits, motor control circuits, etc.
While the drain electrode 133 and the source electrode films 132 are being disconnected from each other, a large voltage may be applied between the drain electrode 133 and the source electrode films 132.
Since the base regions 112 including the channel regions 115 and the conductive layer 106 are reverse-biased while the drain electrode 133 and the source electrode films 132 are being disconnected from each other, the withstand voltage, i.e. the avalanche breakdown voltage, of the MOSFET 101 is determined by the withstand voltage of the PN junction between the base regions 112 and the conductive layer 106.
PN junctions are classified into a planar junction, a cylindrical junction, and a spherical junction according to the shape of a diffusion layer of higher concentration. It is known that the planar junction has a highest withstand voltage and the spherical junction has a lowest withstand voltage.
In the MOSFET 101 composed of the many cells 117, the planar junction is formed at the bottom of each of the cells 117. However, since the cells 117 are polygonal, e.g., rectangular, in shape, the cylindrical junction is necessarily formed at the sides of each of the cells 117 and the spherical junction is necessarily formed at the top of each of the cells 117. The overall withstand voltage is determined by the withstand voltage at the top of each of the cells 117.
It is therefore an object of the present invention to provide a transistor having a high withstand voltage.
Another object of the present invention is to provide a transistor having a low conduction resistance.
To achieve the above objects, there is provided in accordance with the present invention a transistor comprising a semiconductor substrate having a drain layer of a first conductivity type and a withstand voltage region of a second conductivity type disposed on the drain layer, a conductive region of the first conductivity type formed by an impurity partly diffused into the semiconductor substrate from the side of the withstand voltage region side, the conductive region layer of the first conductivity type having a bottom connected to the drain, a base region of the second conductivity type formed by an impurity partly diffused into the semiconductor substrate from the side of the withstand voltage region side, a source region of the first conductivity type formed in the base region, a gate insulating film having a central region positioned on the base region, an end positioned on the conductive region, and an opposite end positioned on the source region, a gate electrode film disposed on the gate insulating film, a channel region positioned between the source region and the conductive region and including a surface of the base region below the gate insulating film, a source electrode electrically connected to the source region and the base region, and a drain electrode electrically connected to the drain layer.
The base region has a surface concentration higher than the surface concentration of the withstand voltage region.
The conductive region has a surface concentration higher than the surface concentration of the withstand voltage region.
The base region has a surface concentration higher than the surface concentration of the conductive region.
The conductive region has a surface surrounded by a region having a conductivity type opposite to the conductivity type of the conductive region.
The base region is diffused from a surface of the withstand voltage region and a surface of the conductive region, and the bottom of the base region has a part in contact with the withstand voltage region and a part in contact with the conductive region.
The base region has a portion positioned within the conductive region and serving as the channel region.
The source region extends between the base region formed in the conductive region and the base region formed in the withstand voltage region.
The base region is diffused from a surface of the withstand voltage region and spaced from the conductive region, the gate insulating film and the gate electrode film being disposed on the surface of the withstand voltage region which is sandwiched between the base region and the conductive region, the channel region includes the surface of the withstand voltage region below the gate insulating film.
The transistor further comprises a low-resistance layer of the first conductivity type disposed on a side of the semiconductor substrate remotely from the withstand voltage region, the low-resistance layer having a concentration higher than the concentration of the drain layer.
The transistor further comprises a collector layer of the second conductivity type disposed on a side of the semiconductor substrate remotely from the withstand voltage region.
With the above arrangement of the present invention, the impurity of the first conductivity type is partly diffused into the withstand voltage region of the second conductivity type through a window defined in a silicon oxide film or the like for thereby forming the conductive region of the first conductivity type in a desired position in the withstand voltage region of the second conductivity type.
The base region of the second conductivity type is partly formed on the withstand voltage region of the second conductivity type by introducing and diffusing the impurity using an oxide film or the like with a window as a mask. When the source region is formed around the base region, the channel region is formed between an outer circumferential end of the base region and the source region. The outer circumferential portion of the base region may be extended into the conductive region or may be spaced from the conductive region.
The bottom of the base region is connected to the withstand voltage region, which includes a projecting portion that projects into a region formed by the drain layer and the conductive region that are of the first conductivity type which is opposite to the conductivity type of the withstand voltage region. Therefore, a depletion layer tends to be spread in the low-concentration withstand voltage region, resulting in a high withstand voltage.
The base region extends into the conductive region. However, since the concentration of the base region is higher than the concentration of the conductive region, if a projecting portion is not disposed as a vertex on the planar shape of the base region in the conductive region, then no spherical junction is formed, resulting in a high withstand voltage.
The conductive region is formed by diffusion. If no spherical junction is present, then the withstand voltage is not relatively lowered even with an increased concentration of the conductive region. Therefore, a low-resistance transistor can be provided.
FIG. 34 of the accompanying drawings is a graph showing the drain-to-source withstand voltage plotted as the surface concentration of the conductive region is varied without changing the diffused structure, and FIG. 35 of the accompanying drawings is a graph showing the conduction resistance per unit area as the withstand voltage is varied.
It can be seen from FIGS. 34 and 35 that while the conduction resistance of the conventional transistor is highly increased when the withstand voltage is increased, the conduction resistance according to the present invention can be reduced even when the withstand voltage is increased.
The above and other objects, features, and advantages of the present invention will become more apparent from the following description when taken in conjunction with the accompanying drawings in which preferred embodiments of the present invention are shown by way of illustrative example.